DocumentCode
3313301
Title
Vertical Power Dissipation Characteristics of Semiconductor Power Devices
Author
Chung, Young S.
Author_Institution
Freescale Semicond. Inc, Tempe
fYear
2007
fDate
27-31 May 2007
Firstpage
241
Lastpage
244
Abstract
A major challenge in the semiconductor power device technology with continuing shrink in feature sizes and its circuit implementation is power density and heat build-up related problems. This paper discusses a significance of vertical power dissipation characteristics of LDMOS devices with investigating electrical and thermal behaviors under single- and multi-power pulse operations in terms of device substrate dimensions.
Keywords
power MOSFET; LDMOS devices; circuit implementation; device substrate dimensions; electrical behavior; multipower pulse operations; power density; semiconductor power devices; single-power pulse operations; thermal behavior; vertical power dissipation characteristics; Automotive engineering; Breakdown voltage; Couplings; Displays; Packaging; Power dissipation; Power measurement; Pulse measurements; Substrates; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on
Conference_Location
Jeju Island
Print_ISBN
1-4244-1095-9
Electronic_ISBN
1-4244-1096-7
Type
conf
DOI
10.1109/ISPSD.2007.4294977
Filename
4294977
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