The effect of wire length minimization on yield

Wire length minimization (WLM) has received significant attention in the compaction stage of VLSI layout synthesis. In most cases, reduction in wire length also results in better circuit yield. However, a trade-off may still exist between total wire length and yield. In WLM only the area/length of the layout patterns is considered whereas for yield enhancement both the area of the layout patterns and the spacing among them must be considered. The trade-off between these two features is analyzed on a set of benchmark layouts in this paper