Synthesis of multi-level self-checking logic

The problem of implementing self-checking combinational circuits is taken into account, with the initial requirement that self-checking capabilities be provided for otherwise optimized multilevel circuits produced by standard CAD tools, without affecting the circuit topology. The solution proposed involves a preliminary reduction of the number of inverters present in the circuit (it is assumed that inverters do not affect the circuit performances as measured by the optimizing CAD tools); then, “pseudo” inputs and outputs are added to the circuit itself in correspondence with the remaining inverters. The virtual circuit thus obtained, with the extended input-output set, is unate and thus grants a uni-directional error model in correspondence of single stuck-at faults. On such circuit a Berger coding policy can be applied, leading to a self-checking circuit covering all single stuck-at faults. Synthesis of the network providing the Berger checkbits is performed by use of Boolean relations