Cost effective testing of systems on silicon: areas for optimization

The advanced silicon technology offers giant numbers of transistors/logic gates to build systems on a chip. These SoCs incorporate logic, memory and mixed signal functions. At the chip periphery we see RF and smart-power interfaces. A lot of research and development on SoC test concentrates on how to achieve sufficient test coverage. We can assume that there will be solutions for complex SoC, which handle IP test integration and reuse with respect to high fault coverage. This paper is intended to stimulate activities, which lead to new cost-effective test solutions that may affect the whole test process.