Resource Constrained Co-synthesis of Self-reconfigurable SOPCs

In this work a co-synthesis method, which allows for optimization of dynamically self-reconfigurable SOPC system architecture, is presented. Partially reconfigurable FPGAs let better use hardware resources due to reuse of the same parts of the chip for different functionalities in the same application. The algorithm maximizes speed of the SOPC system taking into consideration FPGA´s area constraints. The algorithm starts with the initial solution, where all tasks are assigned to only one general purpose processor module. Next it produces new solutions using iterative improvement methods. The reconfiguration times are taken into consideration in task´s scheduling algorithm, in such way, that impact of this time on the system´s performance is minimized. Co-synthesis results for dynamically reconfigurable SOPCs have been compared with the results of co-synthesis which didn´t take into consideration dynamic reconfiguration. Experimental results showed that applying partially reconfigurable FPGAs significantly increases SOPC performance.