Title :
Defect and fault tolerant scan chains
Author :
Kermouche, Rachid ; Savaria, Yvon
Author_Institution :
Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
Abstract :
Several fault tolerant scan chain designs are proposed, including the combinational one data flow and two data flow approaches, and the counter based approach. It is shown that these designs have no critical portion, where a single defect would make the chain inoperative. The yield of these chains is evaluated to show that a long intolerant chain is a predominant yield or harvest detractor, while a tolerant chain becomes an insignificant factor to system yield or harvest
Keywords :
sequential circuits; VLSI; combinational one data flow; combinational two data flow; counter based approach; fault tolerant scan chains; harvest detractor; long intolerant chain; sequential circuit testing; tolerant chain; yield detractor; Application specific integrated circuits; Circuit testing; Control systems; Counting circuits; Fault tolerance; Fault tolerant systems; Integrated circuit testing; Sequential analysis; System testing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
Conference_Location :
Montreal, Que.
Print_ISBN :
0-8186-6307-3
DOI :
10.1109/DFTVS.1994.630029
