Low-Power High-Level Data-Flow Synthesis

A high-level data-flow synthesis method with low power based on Horner form is presented. The function describing of circuit used Horner form is then transformed to get the final polynomial form, to schedule, allocate and binding the data-flow based on Horner form. Reduce power consuming according to reduce the length of interconnect wire and consider the effect of binding and layout in the process of synthesis. A better result is then got under the limit of performance and area. At last an experiment is given and improved its efficiency