Source/drain resistance modeling in bulk and ultra-thin body SOI MOSFETs

Author

Kim, Seong-Dong ; Yuan, Jun ; Woo, Jason C S

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

2005

fDate

7-8 June 2005

Firstpage

99

Lastpage

102

Abstract

In this paper, the optimization of the S/D extrinsic resistance for the recessed and elevated S/D silicide contact structure through physical compact modeling and 2-dimensional TCAD simulation are investigated. A new simplified physical compact modeling is developed and applied to 90-nm SOI CMOS technology to investigate the sub-resistance component contribution and parameter sensitivity. The model-based guideline for the optimum location of silicide/Si interface in elevated S/D structure is proposed with respect to the device parameters including contact size and SOI thickness.

Keywords

MOSFET; electric resistance; elemental semiconductors; semiconductor device models; silicon; silicon-on-insulator; 2-dimensional TCAD simulation; 90-nm SOI CMOS technology; SOI thickness; Si; bulk SOI MOSFET; contact size; device parameters; elevated contact structure; physical compact modeling; recessed contact structure; silicide contact; silicide/Si interface; source/drain resistance modeling; ultrathin body SOI MOSFET; CMOS technology; Contact resistance; Doping profiles; Electric resistance; Immune system; MOSFETs; Remotely operated vehicles; Semiconductor device modeling; Semiconductor process modeling; Silicides;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2005. Extended Abstracts of the Fifth International Workshop on

Print_ISBN

4-9902158-6-9

Type

conf

DOI

10.1109/IWJT.2005.203894

Filename

1598680