Title :
Process design for merged complementary BiCMOS
Author :
Rovedo, N. ; Ogura, S. ; Acocella, J. ; Barnes, K. ; Dally, A. ; Yangisawa, T. ; Ng, C. ; Burkhardt, J. ; Valsamakis, E. ; Hamers, J. ; Buti, T. ; Richwine, C.
Author_Institution :
IBM, Hopewell Junction, NY, USA
Abstract :
A process sequence was designed to fabricate a fully complementary BiCMOS technology. In this technology, a merged bipolar-FET device structure and common subcollector p-n-p are used to implement a complementary emitter follower circuit, yielding a strong density advantage over conventional BiCMOS logic. The problems associated with the p-n-p subcollector formation, gate oxide protection, base formation, emitter protection and source/drain formation have been addressed. The result is a technology with a process complexity that is well-managed and has high performance.<>
Keywords :
BIMOS integrated circuits; integrated circuit technology; protective coatings; IC fabrication; base formation; complementary emitter follower circuit; emitter protection; gate oxide protection; merged bipolar-FET device structure; merged complementary BiCMOS; p-n-p subcollector formation; process sequence; source/drain formation; BiCMOS integrated circuits; Logic circuits; Logic devices; Process design; Protection;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237062
