• DocumentCode
    3317360
  • Title

    Evaluation of eutectic solder bump interconnect technology

  • Author

    Beddingfield, Craig ; Tan, Qing ; Mistry, Addi

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    131
  • Lastpage
    134
  • Abstract
    This paper describes the electroplated solder bump process and provides results from evaluations of the reliability performance and mechanical integrity of the bump interconnect technology for direct chip attach applications. Evaluations include studying the effects of several variables, including (a) the solder bump volume (determined by bump height and diameter), (b) the integrated circuit bond pad configuration (using various passivation opening and under bump metallization diameters), (c) the UBM stud thickness and (d) the underfill material type. The analysis of each of these variables as main effects and, in most cases, interaction effects was achieved by performing mechanical and environmental testing, including solder bump and under bump metallization (UBM) shear strength, die tensile pull, air-to-air temperature cycling (AATC) at a range of -55/125°C and cross-sectional analysis. The intent of this study was to determine the significance of the variables and demonstrate successful reliability performance
  • Keywords
    electroplating; encapsulation; environmental testing; eutectic alloys; flip-chip devices; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; integrated circuit reliability; lead alloys; mechanical testing; passivation; shear strength; soldering; tensile testing; thermal stresses; tin alloys; -55 to 125 C; SnPb; SnPb eutectic bumps; UBM shear strength; UBM stud thickness; air-to-air temperature cycling; bump diameter; bump height; bump interconnect technology; cross-sectional analysis; die tensile pull; direct chip attach applications; electroplated solder bump process; environmental testing; eutectic solder bump interconnect technology; integrated circuit bond pad configuration; interaction effects; mechanical integrity; mechanical testing; passivation opening; reliability performance; solder bump shear strength; solder bump volume; under bump metallization; under bump metallization shear strength; underfill material type; Bonding; Circuit testing; Inorganic materials; Integrated circuit interconnections; Integrated circuit metallization; Integrated circuit reliability; Integrated circuit technology; Passivation; Performance analysis; Performance evaluation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 1999. Twenty-Fourth IEEE/CPMT
  • Conference_Location
    Austin, TX
  • ISSN
    1089-8190
  • Print_ISBN
    0-7803-5502-4
  • Type

    conf

  • DOI
    10.1109/IEMT.1999.804807
  • Filename
    804807