A VHDL based design environment for VLSI circuits

Describes a design environment to model and simulate digital circuits described in VHDL (VHSIC Hardware Description Language). The simulator presented can accept behavioral and data-flow style descriptions. The simulator consists of two primary sections: a front end of the simulator, called an analyzer, and a back-end, called the simulation executive. The analyzer checks for the static errors in the VHDL input description. The analyzer consists of a lexical analyzer, a syntax analyzer, and a semantic analyzer. The lexical analyzer eliminates all the white spaces from the input description; the syntax analyzer checks for VHDL syntax; and the semantic analyzer performs type checking. The simulation executive is directly implemented through the semantic action parts of the lexical analyzer. The simulator´s front-end sections, the scanner and the parser, have been implemented using the automated compiler construction tools LEX and YACC. The results of execution in the test program indicated that the simulator works correctly