DocumentCode
3317533
Title
A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs
Author
Sakao, M. ; Kasai, N. ; Ishijima, T. ; Ikawa, E. ; Watanabe, H. ; Terada, K. ; Kikkawa, T.
Author_Institution
NEC Corp., Tokyo, Japan
fYear
1990
fDate
9-12 Dec. 1990
Firstpage
655
Lastpage
658
Abstract
A novel capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) poly-Si storage node has been developed. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufacturable by optical delineation. The feasibility of the COB cell for 64-Mb DRAMs has been verified by a 64-kb test memory with 1.8- mu m/sup 2/ cells using a 0.4- mu m design rule, storage capacitance of 30 fF, 7-nm-SiO/sub 2/-equivalent dielectric film, and a storage node height of 0.5 mu m.<>
Keywords
DRAM chips; MOS integrated circuits; VLSI; cellular arrays; 0.4 micron; 30 fF; 64 Mbit; COB; COB cell; capacitor-over-bit-line; dielectric film; hemispherical-grain storage node; optical delineation; polysilicon storage node; storage capacitance; storage node height; Capacitance; Dielectric films; Manufacturing; Optical films; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Type
conf
DOI
10.1109/IEDM.1990.237114
Filename
237114
Link To Document