Title :
A pipeline architecture for traffic sign classification on an FPGA
Author :
Yuteng Zhou ; Zhilu Chen ; Xinming Huang
Author_Institution :
Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., Worcester, MA, USA
Abstract :
This paper presents an efficient FPGA design that can classify 48 different traffic signs at real-time. The method is based on histogram of oriented gradients (HOG) feature extraction and support vector machine (SVM) for classification. A full-pipeline, resource efficient architecture is presented with detail design of each block. The FPGA implementation has a system clock of 241.7 MHz with an absolute response time of 6.5 s. Taking streaming pixel input, the system throughput is about 106 times faster than the same algorithm executed on a general purpose processor.
Keywords :
field programmable gate arrays; parallel architectures; pattern classification; pipeline processing; traffic engineering computing; FPGA; HOG; SVM; feature extraction; general purpose processor; histogram of oriented gradients; pipeline architecture; support vector machine; traffic sign classification; Clocks; Computer architecture; Feature extraction; Field programmable gate arrays; Histograms; Random access memory; Support vector machines; FPGA; HOG; SVM; Traffic signs; classification;
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7168792
