Title :
Flip-chip fine package and its assembly line development for GaAs MCM
Author :
Kurata, Hirpyuki ; Ogata, Toshihiro ; Mitsuka, Kaoru ; Matsushita, Hikari ; Kimura, Chikao
Author_Institution :
New Japan Radio Co. Ltd., Kamifukuoka-City, Japan
Abstract :
A newly developed flip-chip fine package (FFP) and its assembly line are presented in this paper. The FFP offers outstanding features such as small size, low profile, low cost, high reliability, low thermal resistance and ease of use, and is suitable for GaAs MMICs used in cellular phones because they require smaller and lighter packages. The developed GaAs MCM FFP has a pin count of 16 with 0.5 mm pitch and package size of 2.5×2.5×0.5 mm in which two GaAs MMICs are flip chip bonded. Ink is directly printed on the exposed backside of a GaAs chip. A 0.25 mm thick Al2O3 ceramic substrate with 59×91 mm area and W-Ni-Au interconnection is used as an array substrate containing 360 pieces of 2.5×2.5 FFP. Au-Au ultrasonic flip chip bonding techniques are applied to connect GaAs chips via 15 μm high Au bumps on bonding pads to the ceramic substrate. This technique has the advantages of reducing bonding temperature, force and time. Use of a ceramic array substrate and the ultrasonic technique is the key to achieving low cost. Some new machines and software are prepared for FFP fabrication. The underfill machine can handle very small quantities of liquid resin. With new software, dicing direction is automatically adjusted to the cutting line, after detecting the substrate shrinkage errors occurred during high temperature co-firing. After dicing, each MCM FFP is picked up, tested and put into the emboss-tape continuously by a machine. Reflow test with JEDEC level-1 -65°C-150°C temperature cycle test and PCT showed no failure. This result means FFP is as reliable as conventional resin mold packages
Keywords :
MMIC; cutting; encapsulation; fine-pitch technology; flip-chip devices; gallium arsenide; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; microassembling; multichip modules; reflow soldering; shrinkage; thermal resistance; ultrasonic bonding; -65 to 150 C; 0.25 mm; 0.5 mm; 15 micron; 2.5 mm; 59 mm; 91 mm; Al2O3; Al2O3 ceramic substrate; Au; Au bumps; Au-Au ultrasonic flip chip bonding techniques; FFP fabrication; GaAs; GaAs MCM; GaAs MCM FFP; GaAs MMICs; GaAs chips; JEDEC level-1 temperature cycle test; PCT; W-Ni-Au; W-Ni-Au interconnection; array substrate; assembly line; assembly line development; bonding force; bonding pads; bonding temperature; bonding time; cellular phones; ceramic array substrate; cutting line; dicing direction; directly printed ink; emboss-tape; exposed GaAs chip backside; flip chip bonded GaAs MMICs; flip-chip fine package; liquid resin; package cost; package profile; package size; packages; pin count; pressure cooker test; reflow test; reliability; substrate shrinkage errors; thermal resistance; ultrasonic technique; underfill machine; Assembly; Bonding; Ceramics; Costs; Gallium arsenide; MMICs; Packaging; Temperature; Testing; Thermal resistance;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1999. Twenty-Fourth IEEE/CPMT
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-5502-4
DOI :
10.1109/IEMT.1999.804822