4-layer 3-D IC technologies for parallel signal processing

A four-layer 3-D device used for parallel image signal processing was fabricated as an example of a primitive 3-D device. SOI (silicon-on-insulator) layers were formed by laser recrystallization. Mesa-type transistors having a stacked dielectric gate insulator were fabricated in a laser recrystallized Si island array. Thermally stable interconnections and contacts were realized by TiSi/sub x/ wiring and TiSi/sub x//TiN/TiSi/sub 2//Si-sub. contact structure. For the interlayer connections, a TiSi/sub x//TiN/W-plug/TiN/TiSi/sub x/ was used. The fabricated 3-D device consists of the following four layers: optical sensor, level-detector, memory, and arithmetic logic unit. The gate length of the SOI transistors is 2 mu m and the deviation of the threshold voltage is 4 approximately 5.5%. The number of transistors is about 110 K.<>