• DocumentCode
    3318396
  • Title

    A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing

  • Author

    Bo Wang ; Leibo Liu

  • Author_Institution
    Inst. of Microelectron., Tsinghua Univ., Beijing, China
  • fYear
    2015
  • fDate
    24-27 May 2015
  • Firstpage
    1182
  • Lastpage
    1185
  • Abstract
    In this paper, a reconfigurable architecture for symmetric ciphers is presented. The InterConnection Tree between Rows (ICTR) reduces the complexity of interconnection based on the data locality of ciphers and finally decreases the area overhead. The Hierarchical Context Organization (HCO) scheme uses an index-based configuration mechanism to avoid the duplication of contexts and accelerate the dynamic configuration. Experimental results show that the architecture is capable of implementing most symmetric ciphers, such as AES, Camellia, DES, SHACAL-1, SMS4, SNOW3G and ZUC, etc. The results also show that it outperforms the state-of-the-art designs in both energy efficiency and area efficiency.
  • Keywords
    cryptography; energy conservation; field programmable gate arrays; integrated circuit interconnections; reconfigurable architectures; AES; Camellia; DES; FPGA; HCO; ICTR; SHACAL-1; SMS4; SNOW3G; ZUC; cipher data locality; energy-efficient reconfigurable architecture; field programmable gate array; hierarchical context organization; index-based configuration mechanism; interconnection tree between row; symmetric cipher processing; Arrays; Ciphers; Context; Energy efficiency; Field programmable gate arrays; Reconfigurable architectures; Reconfigurable crypto architecture; area efficiency; energy efficiency; flexibility; symmetric cipher;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
  • Conference_Location
    Lisbon
  • Type

    conf

  • DOI
    10.1109/ISCAS.2015.7168850
  • Filename
    7168850