Fabrication of photonic devices on Si using pick-and-place multi-wafer technology

There recently has been numerous photonic devices demonstrated that incorporate wafer-bonding in their fabrication. All of these devices however, were fabricated using a single piece of epi-grown wafer to a host substrate. Recently we have demonstrated the first use of pick-and-place technology by using InP multi-quantum-well chips bonded to a GaAs substrate. This pick-and-place process has been extended by using Si as the host wafer instead of GaAs and by further device processing on the individual chips resulting in photonic devices being placed at specific locations on the Si substrate. This technology is desirable since it resolves the wafer size mismatch between small III-V based photonic structures and the Si substrate wafer. The ability to fabricate certain electronic components on the Si host wafer that can withstand the mild bonding conditions of 560°C coupled with the ability to perform multiple bonding procedures using different III-V epi-grown optical structures for various functions will allow for the fabrication of increasingly complex OEIC´s