Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

As device technology is scaling down, ${\rm V}_{\rm th}$ \´s of NAND flash cell show a wide distribution due to process variations such as random dopant fluctuation, etc. Since the extension of ${\rm V}_{\rm th}$ distribution is directly related to degradation of program performance of NAND flash, it is more challenging to meet the market requirements for applications such as solid-state drivers (SSD). This paper presents a novel program scheme, called Adaptive Multi-pulse Program (AMP), for the scaled multi-bit/cell NAND flash devices. In the proposed program scheme memory cells are classified into several groups based on their own program speeds. F-N tunneling characteristic of NAND cell array is considered in determining the level of program bias for each group. Adaptive program pulses are applied to the predefined groups so that cells reach their target verify level at the same time, regardless of the difference of their program speed. Our experimental results show that AMP achieves 20% improvement on program performance due to the reduction of the number of verify executions by 39% in 3-bit/cell architecture NAND flash memory of 21 nm CMOS technology.