Abstract :
Present microcomputer technology, is not sufficiently powerful enough to perform real-time (approximately 100 iterations per second) reconstruction of quantitative tomographic electrical impedance tomography images. Specialised parallel computers designed to perform matrix manipulation efficiently have to be used for matrix manipulation problems, particularly sequential processes such as matrix multiplication, the wavefront array processor (WAP) is considered to be one of the most efficient parallel computer architectures. However, this configuration is not particularly efficient when the processing array is small (<3%) compared to the data matrix, and is therefore usually implemented in VLSI to keep the array large and cost low. A more superior architecture and combined matrix multiplication algorithm which can deliver up to five times more computing power than the WAP was developed by the authors. Together with this novel architecture, the paper also compares its efficiency with some of the more common commercial computers and co-processor accelerator cards
