• DocumentCode
    3320388
  • Title

    Instruction Selection in ASIP Synthesis Using Functional Matching

  • Author

    Arora, Nidhi ; Chandramohan, Kiran ; Pothineni, Nagaraju ; Kumar, Anshul

  • Author_Institution
    CSE Dept, IT Delhi, New Delhi, India
  • fYear
    2010
  • fDate
    3-7 Jan. 2010
  • Firstpage
    146
  • Lastpage
    151
  • Abstract
    In embedded systems, Application Specific Instruction Set Processors (ASIPs) are used commonly with the aim to get high performance without losing flexibility. A crucial operation required during ASIP synthesis (in particular, selection of custom instructions) as well as code generation for ASIPs is identifying portions of an application program that can be executed by custom functional units (CFUs). Most existing solutions achieve this by matching structure of patterns corresponding to CFUs with sub-graphs of application data flow graphs. Often it happens that the computations performed by the two are equivalent, but due to structural dissimilarities the match is missed. What is needed is a method that can match two graphs functionally rather than structurally. In this paper, we present a novel method to do this and give implementation results to show its effectiveness.
  • Keywords
    application specific integrated circuits; data flow graphs; embedded systems; instruction sets; logic design; ASIP synthesis; application specific instruction set processors; code generation; custom functional units; data flow graphs; embedded systems; functional matching; instruction selection; pattern matching; Application specific processors; Computer aided instruction; Computer applications; Computer networks; Embedded computing; Embedded system; Flow graphs; Pattern matching; Routing; Very large scale integration; ASIP; Confluence; Covering; Functional Matching; Structural Matching;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2010. VLSID '10. 23rd International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4244-5541-6
  • Type

    conf

  • DOI
    10.1109/VLSI.Design.2010.68
  • Filename
    5401277