• DocumentCode
    3320844
  • Title

    An efficient processor for joint barrel distortion correction and color demosaicking

  • Author

    Hui-Sung Jeong ; Tae-Hwan Kim

  • Author_Institution
    Sch. of Electron., Telecommun. & Comput. Eng., Korea Aerosp. Univ., Goyang, South Korea
  • fYear
    2015
  • fDate
    24-27 May 2015
  • Firstpage
    1782
  • Lastpage
    1785
  • Abstract
    This paper presents an efficient hardware architecture to perform the real-time correction of the barrel distortion in wide-angle cameras. Applied to the single-sensor cameras employing the Bayer pattern as the color filter array (CFA), the proposed architecture performs the backward mapping process once for each pixel location in the Bayer pattern and the sub-pixel image resampling process for each color channel considering the CFA. As a result, the proposed architecture performs the barrel distortion correction jointly with the color demosaicking effectively. A prototype of the BDC processor based on the proposed architecture is implemented with 53.3K logic gates in a 0.18μm CMOS technology and its correction speed is 311M pixels/s, which shows that the proposed architecture has low complexity even with such versatile functionality.
  • Keywords
    filtering theory; image colour analysis; image segmentation; BDC processor; Bayer pattern; CFA; CMOS technology; color filter array; joint barrel distortion correction and color demosaicking; sub-pixel image resampling process; wide-angle cameras; Cameras; Color; Complexity theory; Distortion; Hardware; Image color analysis; Interpolation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
  • Conference_Location
    Lisbon
  • Type

    conf

  • DOI
    10.1109/ISCAS.2015.7169000
  • Filename
    7169000