Title :
NMOS realization of ternary functions with digital summation threshold gates
Author :
Razavi, Hassan M.
Author_Institution :
Dept. of Comput. Sci., North Carolina Univ., Charlotte, NC, USA
Abstract :
An NMOS circuit realization is proposed for ternary functions based on a digital summation threshold gate. The procedure is systematic and any ternary function can be realized with a single gate. Many ternary functions were realized and the resulting circuits were simulated using the MCNC (Microelectronics Center for North Carolina) tools for VLSI design. The speed and complexity of the gate depend on the weighed sum for a given function
Keywords :
VLSI; circuit CAD; circuit analysis computing; field effect integrated circuits; integrated logic circuits; logic CAD; ternary logic; CAD; MCNC tools; Microelectronics Center for North Carolina; NMOS realization; VLSI design; circuit simulation; digital summation threshold gates; logic ICs; logic design; ternary functions; weighed sum; Circuit simulation; Computer science; Integrated circuit interconnections; MOS devices; Microelectronics; Multivalued logic; Very large scale integration; Voltage; Wire; Wiring;
Conference_Titel :
Southeastcon '89. Proceedings. Energy and Information Technologies in the Southeast., IEEE
Conference_Location :
Columbia, SC
DOI :
10.1109/SECON.1989.132447
