DPLL with hybrid ΔΣ phase/frequency detector

Digital phase-locked loop (PLL) with dynamic hybrid Delta-Sigma (ΔΣ) phase/frequency detector (PFD). It combines the benefits of a traditional analog charge-pump-based PLL and a modern time-to-digital converter (TDC)-based all-digital PLL, namely, infinite phase-error detection resolution and all-digital control of a digitally controlled oscillator, respectively. An Lth-order ΔΣ analog-to-digital converter (ADC) implements an (L+1)-order ΔΣ PFD via closed-loop frequency detection. Fine resolution encoding of the ΔΣ PFD output facilitates multi-bit phase/frequency error digitization. A spur-free, wide bandwidth DPLL with a hybrid 2nd-order ΔΣ PFD that is based on a 1st-order continuous-time multi-bit ΔΣ ADC is presented in this paper. Low analog implementation complexity is achieved via digital noise-shaping requantization and noise cancellation.