Optimized hardware architecture of a smart camera with novel cyclic image line storage structures for morphological raster scan image processing

In this work we present an FPGA (Field Programmable Gate Array) based smart camera framework with a multiport cyclic image line storage structure and an optimized architecture for morphological raster scan image processing. The signal processing architecture is able to reuse intermediate results of 2D morphological operations, can handle different shapes of structuring elements and uses only a minimum amount of FPGA logic and block RAM resources for intermediate image line storage. This combination allows the output of one processed pixel per clock cycle and hence, build the fundament for a system architecture, which provides high frame rates with low system delays.