50-MHz phase locked loop with adaptive bandwidth for jitter reduction

This paper presents an analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. The relationships of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL is described in detail and a prototype 50 MHz PLL in a 0.18 - mum CMOS technology is tested.