DocumentCode :
332687
Title :
On accelerating pattern matching for technology mapping
Author :
Matsunaga, Y.
Author_Institution :
Fijitsu Labs. Ltd., Japan
fYear :
1998
fDate :
8-12 Nov. 1998
Firstpage :
118
Lastpage :
123
Abstract :
The pattern matching algorithm is simple and fast compared to other such matching algorithms such as Boolean matching. One major drawback of the pattern matching is that there is a case where a cell needs a lot of patterns representing its logic function. That is because patterns are decomposed into 2-AND/NOT patterns to match against decomposed subject graphs. Furthermore, the conventional technology mapper does not pay much attention to relations among patterns. Each pattern is tried to match independently. A novel pattern matching algorithm that does not require patterns to be decomposed and couple speeding up techniques utilizing inter-relations among cells are described. These methods are very effective for large cell libraries with complex cells. Experimental results show that our methods gain matching time up to 40 times faster.
Keywords :
logic CAD; logic gates; pattern matching; AND/NOT patterns; complex cells; decomposed subject graphs; inter-relations; large cell libraries; logic function; matching time; novel pattern matching algorithm; pattern matching; pattern matching algorithm; technology mapper; technology mapping; Acceleration; Inverters; Laboratories; Libraries; Logic functions; Pattern matching; Permission;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-008-2
Type :
conf
DOI :
10.1109/ICCAD.1998.144254
Filename :
742860
Link To Document :
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