Title :
A performance-driven layer assignment algorithm for multiple interconnect trees
Author :
Saxena, P. ; Liu, C.L.
Author_Institution :
Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
With the advent of DSM technologies, interconnect delays increasingly overshadow the transistor delays. Furthermore, since the electrical characteristics of different layers in multilayer routing technologies vary widely, the assignment of the interconnect tree edges to specific routing layers has a large impact on the interconnect delays. Traditionally, critical global interconnect trees were routed greedily, one at a time. This caused the "good" layers to be used up largely for the first few trees, yielding poor routings for the remaining trees. Multiple passes with different tree orderings were usually used to remedy the situation, although with limited success. We propose the use of dynamically adjusted area quotas to prevent the first few trees from monopolizing the "good" layers. Our approach is independent of the routing model or the router employed, and reduces the maximum tree delays by around 15% as compared to traditional algorithms.
Keywords :
circuit CAD; delays; interconnections; trees (mathematics); DSM technologies; critical global interconnect trees; deep sub-micron; dynamically adjusted area quotas; electrical characteristics; interconnect delays; interconnect tree edges; maximum tree delays; multilayer routing technologies; multiple interconnect trees; multiple passes; performance driven layer assignment algorithm; routing layers; routing model; transistor delays; tree orderings; Computer science; Costs; Delay; Electric variables; Permission; Routing;
Conference_Titel :
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-008-2
DOI :
10.1109/ICCAD.1998.144255