Biasing technique for reduced process and temperature variations of high speed, low power switched capacitor circuits

A biasing technique that minimizes the process and temperature variations of the slew rate and the gain bandwidth product of the amplifiers at the core of any switched capacitor circuit is presented. It is based on using a switched capacitor current reference coupled with weak inversion biasing of the input differential pair of the amplifier. A minimum value for the inversion coefficient that maximizes the transconductance efficiency without compromising the parasitic capacitance at the amplifier´s input is analytically derived. The proposed biasing circuit is analyzed and designed using a 130 nm CMOS process. The performance was verified by simulations with a high speed telescopic OTA.