CMOS analog circuit stack generation with matching constraints

An efficient CMOS transistor stack generation procedure for analog circuits is described. The matching requirements are used as the primary constraint on the analog layout, however, parasitic capacitances and area considerations are also included. A designer chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intra-module connectivity. The port structures are considered as part of the module area and parasitic optimization procedure. The results are demonstrated through an example and a complete chip layout of a high-resolution delta-sigma analog-to-digital converter.