Proposal of a timing model for CMOS logic gates driving a CRC /spl pi/ load

We present a gate delay model of CMOS logic gates driving a CRC /spl pi/ load for deep sub-micron technology. Our approach is to replace series-parallel connected MOSFETs to an equivalent MOSFET and calculate the output waveform by an analytically derived formula. We present a MOSFET drain current model improved from the n-th power law MOSFET model to represent the characteristic of the equivalent inverter accurately. The accuracy of our gate delay model is evaluated in several gates under various conditions of input transition time and CRC parameters. The maximum error is less than 10.3% in the experiments. Our approach contributes to fast and accurate estimation of circuit speed under various supply voltage, which will enable us to optimize the circuit speed and power dissipation.