DocumentCode
332782
Title
Symbolic model checking of process networks using interval diagram techniques
Author
Strehl, K. ; Thiele, L.
Author_Institution
Comput. Eng. & Networks Lab., Fed. Inst. of Technol., Zurich, Switzerland
fYear
1998
fDate
8-12 Nov. 1998
Firstpage
686
Lastpage
692
Abstract
In this paper, an approach to symbolic model checking of process networks is introduced. It is based on interval decision diagrams (IDDs), a representation of multi-valued functions. Compared to other model checking strategies, IDDs show some important properties that enable the verification of process networks more adequately than with conventional approaches. Additionally, applications concerning scheduling are shown. A new form of transition relation representation called interval mapping diagrams (IMDs)-and their less general version predicate action diagrams (PADs)-are explained together with the corresponding methods.
Keywords
decision diagrams; formal verification; logic CAD; scheduling; interval decision diagrams; interval mapping diagrams; multi-valued functions; predicate action diagrams; process networks; scheduling; symbolic model checking; transition relation representation; Boolean functions; Computer networks; Data structures; Dynamic scheduling; Formal verification; Job shop scheduling; Network synthesis; Permission; Processor scheduling; System recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
Print_ISBN
1-58113-008-2
Type
conf
DOI
10.1109/ICCAD.1998.144343
Filename
743097
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