An interconnection architecture for integrate and fire neuromorphic multi-chip networks

The availability of large neuromorphic electronic systems can represent a really useful tool to deeply and effectively investigate on innovative, "bio-inspired", computational paradigms. Among the others, one of the main obstacles in implementation of large networks is represented by the limited silicon area available on a chip that requires further efforts to design interconnected architectures. A particular strategy to reduce the I/O analogue pins well suited for neuromorphic multi chip architecture will be presented.