Title :
Bi-level image high speed code conversion processor: ImPC2
Author :
Horie, Hitoshi ; Shirai, Hideyuki ; Iizuka, Yasuo ; Takahata, Minoru
Author_Institution :
Matsushita Graphic Commun. Syst. Inc., Tokyo, Japan
Abstract :
This paper describes a very high speed coding and decoding processor, Image Pipeline Codec 2 (ImPC2), which includes the redundancy reduction coding algorithms: Modified Huffman (MH), Modified RAED (MR), Modified MR (MMR) and JBIG. The ImPC2 architecture combines pipeline and parallel processing. The ImPC2 contains a resolution conversion unit, a DMA controller, 4096×16-bit RAM, and a microprogram controller with 4096×50-bit program ROM, as well as a specific encoder and decoder for MH, MR, MMR and JBIG. The ImPC2 chip is fabricated using 0.6 micron CMOS technology, integrating approximately 1,060,000 transistors on a 9.17 mm×8.50 mm die
Keywords :
CMOS digital integrated circuits; Huffman codes; VLSI; code convertors; decoding; digital signal processing chips; high-speed integrated circuits; image coding; microprogramming; parallel architectures; pipeline processing; redundancy; 0.6 micron; 20 MHz; 400 mW; DMA controller; ImPC2 architecture; Image Pipeline Codec 2 chip; JBIG algorithm; RAM; bi-level image processor; high speed code conversion processor; microprogram controller; modified Huffman algorithm; modified RAED algorithm; parallel processing; pipeline processing; program ROM; redundancy reduction coding algorithms; resolution conversion unit; submicron CMOS technology; very high speed coding; very high speed decoding; CMOS technology; Codecs; Decoding; Facsimile; Image coding; Image converters; Image resolution; Parallel processing; Pipelines; Read-write memory;
Conference_Titel :
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location :
Chiangmai
Print_ISBN :
0-7803-5146-0
DOI :
10.1109/APCCAS.1998.743895
