VLSI architecture for significance map coding of embedded zerotree wavelet coefficients

In this paper, we present a hardware architecture to implement the significance map coding for the embedded zerotree wavelet (EZW) algorithm. The architecture is regular and modular and is suitable for VLSI implementation. The approach is based on developing an efficient scheme to determine ancestor-descendant relationships in the wavelet coefficient data stream by rearrangement of the data stream for simpler VLSI implementation. The significance map coding for the EZW algorithm is formulated in view of the rearranged data stream and the corresponding VLSI architecture to implement the formulated requirements is presented