Title :
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration
Author :
Zaidi, Izhar ; Nabina, Atukem ; Canagarajah, CN ; Nunez-Yanez, Jose
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Bristol, Bristol
Abstract :
This paper explores the utilization of run-time partial dynamic reconfiguration in the LEON3 open-source soft core processor, which is a highly configurable SPARC (scalable processor architecture) V8 instruction set processor. The work explores the possibilities of sharing different arithmetic functions tightly coupled to the integer pipeline and mapped to the same silicon area, saving power consumption and area utilisation. The same strategy can be used to extend the instruction set architecture of the processor with new instructions that are optimized for DSP applications. The logic necessary to support these instructions could then be swapped as demanded by the application.
Keywords :
field programmable gate arrays; microprocessor chips; DSP applications; FPGA-based open-source processor; LEON3 open-source soft core processor; V8 instruction set processor; arithmetic functions; configurable SPARC; integer pipeline; partial dynamic reconfiguration; power-area analysis; scalable processor architecture; Clocks; Control systems; Costs; Delay; Energy consumption; Fabrics; Field programmable gate arrays; Hardware; Open source software; Pipelines; Internal Configuration access Port; Leon3; Partial Dynamic Reconfiguration;
Conference_Titel :
Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on
Conference_Location :
Parma
Print_ISBN :
978-0-7695-3277-6
DOI :
10.1109/DSD.2008.92