A Variable Length Vector Pipeline Architecture Design Methodology

The architecture design phase is one of the most important steps in the system LSI development process. In this paper, we propose a C-based pipeline architecture design methodology and apply it to the design of the output probability computation circuit for a real time speech recognition system. Several variable length vector pipeline architectures accelerated by loop optimization, memory access optimizations, and application-specific circuit design were implemented to calculate the hidden Markov model (HMM) output probability at high speed and their performances evaluated.