Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification

Hardware Accelerated Simulation is widely used in validation of complicated hardware designs. The process of designing a circuit consists of writing the HDL code, and writing and applying the testbenches to the design. Unfortunately, testbenches are often not synthesizable and cannot be used in hardware accelerated simulation. In this paper we propose a method to convert an existing non-synthesizable testbench to a synthesizable one, and apply it to some case studies to show its effectiveness in the hardware accelerated simulation.