Interconnect technique for sub-threshold circuits using negative capacitance effect

Global interconnects in deep-submicron (DSM) regime contribute a significant amount of power consumption and large propagation delay. As the global interconnect delay dictating the overall system performance, its variation also has larger impact on system performance in sub-threshold circuits. Due to the exponential relationship between weak-inversion current and the process-voltage-temperature (PVT) parameters, performance and power dissipation of sub-threshold circuits are exceedingly sensitive to PVT fluctuations. In order to build efficient sub-threshold circuits with higher operating frequencies, it is crucial to minimize the global interconnect delay and its variation. Shifting the interconnect driver transistors from the sub-threshold region to the super-threshold region is a way to secure a high-speed variation-tolerant interconnect system for sub-threshold circuits. Standard MOSFET with a ferroelectric insulator exhibits negative capacitance effect at low voltage and provides a lower than 60 mV/dec swing. Therefore, it is more suitable for sub-threshold operation than bulk CMOS, and it can boost the applied gate voltage internally and results show a boosting efficiency of 100% could be obtained at a supply voltage of 0.2 volts. Besides, impact of process variation on sub-threshold operation with MOSFET with a ferroelectric insulator is also mentioned.