An efficient on-line-test and back-up scheme for embedded processors

Self-test strategies for processors in embedded core-based systems have recently found great attention for two reasons. First, production test for embedded cores is becoming a problem due to inaccessible processor pins. Second, self-test is a very desirable feature for processors in applications that require a high level of dependability over a long life time. Standard processors or processor-cores used in embedded systems are not accessible for a full-scale redesign. Therefore methods must be developed that facilitate self-test by keeping the original cores as unharmed as possible. The approach presented here duplicates only the truly necessary parts of a standard processors for test and back-up purposes including capabilities of on-line self-test. Transient faults are recognized and compensated. In a second step, the back-up processor itself becomes fully self-testing and fault tolerant towards a highly dependable system solution by state-encoding of control paths and Berger code check in the data path