Title :
Design for test and time to market-friends or foes
Author_Institution :
SynTest Technol. Inc., USA
Abstract :
This paper describes the interactions between early decisions made regarding design for testability and their impact during the product design and test development phases of a product´s life cycle on overall time to market for the product
Keywords :
automatic testing; built-in self test; design for testability; integrated circuit testing; logic testing; product development; ATPG; VHDL; design for testability; product design; product development; product´s life cycle; system on chip design; test development; time to market; Built-in self-test; Circuit faults; Circuit testing; Controllability; Costs; Delay; Design for testability; Life testing; Product design; Time to market;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805844
