Low-complexity integrated architecture of 4×4, 4×8, 8×4 and 8×8 inverse integer transforms of VC-1

During decoding the bit stream of a block, only a block type selecting from 4times4, 4times8, 8times4 and 8times8 is employed to do the inverse integer transform of VC-1. Accordingly, the hardware architectures of 4times4, 4times8, 8times4 and 8times8 inverse integer transforms can be integrated to reduce hardware cost. In this work, a low-complexity integrated hardware architecture is proposed to realize these four inverse integer transforms. First, the one-dimensional transform operations associated with 4 and 8 points are analyzed to find out the common parts. Second, the transform multiplications are decomposed into multiple additions and shifting operations due to the fixed transform coefficients. The one-dimensional transform architecture that integrates adders and shifters of 4-point and 8-point operations with multiplexers and registers is developed at a regular data-flow manner. Finally, four 4times4, two 4times8, two 8times4 and one 8times8 transforms can be individually computed in the proposed integrated one-dimensional transform architecture under 16 clock cycles. As compared to the conventional architecture which implements 4-point and 8-point inverse integer transforms separately, the proposed architecture consumes less hardware cost to accomplish the inverse integer transform(s) of a block at a specific throughput rate.