Design of a digital VLSI neuroprocessor for signal and image processing

Author

Chang, Chia-Fen ; Sheu, Bing J.

Author_Institution

Dept. of Electr. Eng., Signal & Image Process. Inst., Univ. of Southern California, Los Angeles, CA, USA

fYear

1991

fDate

30 Sep-1 Oct 1991

Firstpage

606

Lastpage

615

Abstract

An efficient processing element for data/image processing has been designed. Detailed communication networks, instruction sets and circuit blocks are created for ring-connected and mesh-connected systolic arrays for the retrieving and learning phases of the neural network operations. 800 processing elements can be implemented in 3.75 cm×3.75 cm chip by using the 0.5 μm CMOS technology from TRW, Inc. This digital neuroprocessor can also be extended to support fuzzy logic inference

Keywords

CMOS integrated circuits; VLSI; digital signal processing chips; fuzzy logic; image processing; neural chips; signal processing; systolic arrays; 0.5 micron; CMOS technology; circuit blocks; communication networks; digital VLSI neuroprocessor; digital neuroprocessor; fuzzy logic inference; image processing; instruction sets; learning phases; mesh-connected systolic arrays; retrieving phases; signal processing; CMOS technology; Circuits; Communication networks; Image processing; Instruction sets; Neural networks; Process design; Signal design; Systolic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks for Signal Processing [1991]., Proceedings of the 1991 IEEE Workshop

Conference_Location

Princeton, NJ

Print_ISBN

0-7803-0118-8

Type

conf

DOI

10.1109/NNSP.1991.239480

Filename

239480