• DocumentCode
    3333371
  • Title

    Dense layouts for series-parallel circuits

  • Author

    Langston, Michael A. ; Ramachandramurthi, Siddharthan

  • Author_Institution
    Dept. of Comput. Sci., Tennessee Univ., Knoxville, TN, USA
  • fYear
    1991
  • fDate
    1-2 Mar 1991
  • Firstpage
    14
  • Lastpage
    17
  • Abstract
    The authors address the question `when do three tracks suffice for the gate matrix layout of series-parallel circuits?´ and demonstrate that the rather surprising answer appears to be `almost always.´ This is in contrast to the fact that an unbounded number of tracks may be required to layout contrived instances in the worst case. Their approach stems from the novel nonconstructive finite-basis characterization of graphs with k-track layouts for any fixed k
  • Keywords
    VLSI; circuit layout CAD; graph theory; network topology; gate matrix layout; graphs; nonconstructive finite-basis characterization; series-parallel circuits; Computer science; Contracts; Frequency locked loops; Heart; Heuristic algorithms; Integrated circuit layout; Polynomials; Random number generation; Testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1991. Proceedings., First Great Lakes Symposium on
  • Conference_Location
    Kalamazoo, MI
  • Print_ISBN
    0-8186-2170-2
  • Type

    conf

  • DOI
    10.1109/GLSV.1991.143935
  • Filename
    143935