VLSI architecture for an advance DS/CDMA wireless communication receiver

This paper presents an efficient VLSI Architecture for an advanced Direct Sequence CDMA Wireless Communication Receiver. Compensating for near/far effects is critical for the satisfactory performance of D/S CDMA systems. An effective approach to combat the near/far effect is multi-user detection. This approach has the potential of increasing the capacity by canceling co-channel interference. The receiver discussed here operates by successively canceling user interferences ranked in order of received power levels. The ranking is obtained from the (magnitude of) the correlations of user chip sequences with the received signal. We present an efficient VLSI architecture for its implementation. Further, we show that the performance of this receiver is vastly superior to the conventional receiver (without cancellation)