Title :
Architecture, defect tolerance, and buffer design for a new ATM switch
Author :
Jain, V.K. ; Lin, L. ; Horiguchi, S.
Author_Institution :
Univ. of South Florida, Tampa, FL, USA
Abstract :
This paper presents a modular architecture for a scalable ATM-switch. The cell routing function, and the associated queueing, is distributed over many small clusters of nodes, called basic modules. These basic modules are hierarchically interconnected to form larger switches. In a basic module, every node is interconnected with adjacent nodes in the same module with three of its four links. The fourth link is used to connect either to external ports or to other basic modules at higher levels of the hierarchy. From a hardware implementation perspective, the simplicity of the architecture stems from the fact that each node in the switch consists of two small crossbar switches of low complexity and a buffer, plus a controller. The hierarchial nature of the topology allows for modular growth of the switch. Further, the interconnection topology of the switch makes it suitable for 3-D (stacked VLSI/WSI) implementation
Keywords :
B-ISDN; asynchronous transfer mode; integrated circuit interconnections; packet switching; telecommunication network routing; wafer-scale integration; 3D implementation; adjacent nodes; basic modules; buffer design; cell routing function; crossbar switches; defect tolerance; hierarchical interconnection; modular architecture; scalable ATM-switch; stacked VLSI/WSI; Asynchronous transfer mode; Bit rate; Communication switching; Electronic mail; Hardware; Quality of service; Routing; Switches; Telecommunication network topology; Telecommunication traffic;
Conference_Titel :
Innovative Systems in Silicon, 1997. Proceedings., Second Annual IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-4276-3
DOI :
10.1109/ICISS.1997.630267