Logical clustering for fast clock skew scheduling

Clock skew scheduling (CSS) is an effective approach to improve the circuit frequency in synchronous circuits. Most previous works about CSS were based on individual registers, but they suffered from scaling problems for large designs. To alleviate this problem, we introduce a novel abstract layer called logical cluster instead of traditional register. A bounded logical clustering method based on timing relation (TRLC) is proposed to reduce the number of independent nodes, and then the tradeoff between aggregation degree and potential upper bound of optimal frequency is analyzed. Furthermore, a bus group logical clustering method (BGLC) is presented to achieve higher aggregation if additional logic information is available. Our experiments show that our approaches achieve significant reduction for the input size of CSS problem even by orders of magnitude, and derive a superlinear or even exponential speedup in runtime.