Consideration for CDM breakdown and reliability designing in the latest semiconductor technology

CDM (charged device model) is still concerned reliability topic of ESD (electrostatic discharge). ESD breakdown voltage tends to lower with Silicon technology down scaling because of lack of energy change in source of ESD stress. Severity for the recent device and reality for actual situation are the reasons why many engineers are investigating aggressively. Fundamental consideration for CDM (charged device model) in the point of breakdown and reliability designing were investigated with the recent semiconductor technology to achieve good endurant device for CDM. According to the result of failure analysis for CDM failed semiconductor device, it was found that gate oxide breakdown was critical failure mode in CDM. For the parameters investigation, Peak intensity and rise time of discharge current are well correlated their package capacitance. To consider this discharge phenomenon in the points of protection circuit, device and package is effective method to achieve well reliable design for CDM breakdown. Moreover there is further investigation. Increasing zapping time in CDM test causes breakdown voltage lowering, which mechanism is similar to that of TDDB for gate oxide breakdown. There is a tendency that an enlargement of semiconductor product scale which is represented with increasing of IC-pin number raises total zapping times in CDM test. Then, excessive CDM zapping stress accumulates its damage into critical gate oxide film and causes breakdown by lower voltage. This phenomenon might be near future concern. These result and consideration from our experiences are explained in this report.