Development of a hybrid CdTe pixel detector with a low-noise front-end ASIC

We have developed a prototype cadmium telluride (CdTe) pixel detector for future use in focusing hard X-ray telescopes. We adopted a hybrid configuration where each CdTe sensor pixel is vertically connected to a corresponding pixel cell fabricated in a readout ASIC. This configuration is suitable for detectors with high pixel density to reduce a stray capacitance between readout signal lines. The readout chip consists of a 12 × 12 matrix of identical 270 ¿m × 270 ¿m pixel cells, and was implemented with TSMC 0.35-¿m CMOS technology. Each pixel cell contains a charge-sensitive amplifier, pole-zero cancellation circuit, low-pass filter, comparator, and peak/bottom-hold circuit. We succeeded to obtain detector signals from all the 144 channels, showing a equivalent noise charge distribution of 66±4 e (rms). The linearity is maintained within ±1 % up to 3.5 fC, which corresponds to ~ 100 keV for CdTe. The detector exhibits good spectral performance with 870 eV (FWHM) at 59.5 keV. The power consumption is 150 ¿W per pixel, and 48 mW in total.