DocumentCode
3334253
Title
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits
Author
Kajihara, Seiji ; Pomeranz, Irith ; Kinoshita, Kozo ; Reddy, Sudhakar M.
Author_Institution
Dept. of Applied Physics, Osaka University, Suita, Japan
fYear
1993
fDate
14-18 June 1993
Firstpage
102
Lastpage
106
Abstract
New cost-effective heuristics for the generation of small test sets are introduced, and heuristics proposed previously are enhanced. An improved procedure is also proposed for computing independent fault sets which are used to selecet target faults in test generation. The procedure results in large lower bounds on the minimum test set size. Experimental results of test generation demonstrate the effectiveness of the heuristics.
Keywords
Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Electrical fault detection; Fault detection; Flip-flops; Logic testing; Physics computing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1993. 30th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-577-1
Type
conf
DOI
10.1109/DAC.1993.203927
Filename
1600200
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