A modified charging algorithm for comparator-based switched-capacitor circuits

Author

Wong, Kim-Fai ; Sin, Sai-Weng ; Seng-Pan U ; Martins, R.P.

Author_Institution

Analog & Mixed-Signal VLSI Lab., Univ. of Macau, Macao, China

fYear

2009

fDate

2-5 Aug. 2009

Firstpage

86

Lastpage

89

Abstract

This paper presents a modified charging algorithm for fully-differential comparator-based switched-capacitor (CBSC) circuits by utilizing an additional comparator to compare a variable differential threshold rather than detecting the zero crossing during coarse (E₁) transfer phase. The large overshoot in the coarse phase can be eliminated such that it relaxes the stringent trade-off between speed and accuracy, which exists in the conventional CBSC circuits. A 1.2-V Sample-and-Hold circuit implemented in 90 nm CMOS process is used to demonstrate the effectiveness of this concept.

Keywords

CMOS analogue integrated circuits; comparators (circuits); sample and hold circuits; switched capacitor networks; CMOS process; charging algorithm; comparator-based switched-capacitor circuit; fully-differential CBSC circuit; sample-and-hold circuit; size 90 nm; voltage 1.2 V; CMOS technology; Charge transfer; Circuit simulation; Phase detection; Sampling methods; Switched capacitor circuits; Switches; Switching circuits; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Conference_Location

Cancun

ISSN

1548-3746

Print_ISBN

978-1-4244-4479-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2009.5236147

Filename

5236147